The present invention relates to semiconductor switching devices, and more particularly to switching devices for power switching and power amplification applications and methods of forming same.
Power MOSFETs have typically been developed for applications requiring power switching and power amplification. For power switching applications, the commercially available devices are typically DMOSFETs and UMOSFETs. In these devices, one main objective is obtaining a low specific on-resistance to reduce power losses. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion-layer channel (also referred to as xe2x80x9cchannel regionxe2x80x9d) is formed in the P-type base region in response to the application of a positive gate bias. The inversion-layer channel electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween.
The power MOSFET""s gate electrode is separated from the base region by an intervening insulating layer, typically silicon dioxide. Because the gate is insulated from the base region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET""s base region. Thus, only charging and discharging current (xe2x80x9cdisplacement currentxe2x80x9d) is required during switching. Because of the high input impedance associated with the insulated-gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Moreover, because current conduction in the MOSFET occurs through majority carrier transport through an inversion-layer channel, the delay associated with the combination and storage of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors. Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as xe2x80x9csecond breakdownxe2x80x9d. Power MOSFETs can also be easily paralleled, because the forward voltage drop across power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices.
DMOSFETs and UMOSFETs are more fully described in a textbook by B. J. Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (ISBN 0-534-94098-6) (1995), the disclosure of which is hereby incorporated herein by reference. Chapter 7 of this textbook describes power MOSFETs at pages 335-425. Examples of silicon power MOSFETs including accumulation, inversion and extended trench FETs having trench gate electrodes extending into the N+ drain region are also disclosed in an article by T. Syau, P. Venkatraman and B. J. Baliga, entitled Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Convention UMOSFETs, IEEE Transactions on Electron Devices, Vol. 41, No. 5, May (1994). As described by Syau et al., specific on-resistances in the range of 100-250 xcexcxcexa9cm2 were experimentally demonstrated for devices capable of supporting a maximum of 25 volts. However, the performance of these devices was limited by the fact that the forward blocking voltage must be supported across the gate oxide at the bottom of the trench. U.S. Pat. No. 4,680,853 to Lidow et al. also discloses a conventional power MOSFET that utilizes a highly doped N+ region 130 between adjacent P-base regions in order to reduce on-state resistance. For example, FIG. 22 of Lidow et al. discloses a high conductivity region 130 having a constant lateral density and a gradient from relatively high concentration to relatively low concentration beginning from the chip surface both the gate oxide and extending down into the body of the chip.
FIG. 1(d) from the aforementioned Syau et al. article discloses a conventional UMOSFET structure. In the blocking mode of operation, this UMOSFET supports most of the forward blocking voltage across the N-type drift layer, which must be doped at relatively low levels to obtain a high maximum blocking voltage capability, however low doping levels typically increase the on-state series resistance. Based on these competing design requirements of high blocking voltage and low on-state resistance, a fundamental figure of merit for power devices has been derived which relates specific on-resistance (Ron,sp) to the maximum blocking voltage (BV). As explained at page 373 of the aforementioned textbook to B. J. Baliga, the ideal specific on-resistance for an N-type silicon drift region is given by the following relation:
Ron,sp=5.93xc3x9710xe2x88x929(BV)2.5xe2x80x83xe2x80x83(1) 
Thus, for a device with 60 volt blocking capability, the ideal specific non-resistance is 170 xcexcxcexa9cm2. However, because of the additional resistance contribution from the channel, reported specific on-resistances for UMOSFETs are typically much higher. For example, a UMOSFET having a specific on-resistance of 730 xcexcxcexa9cm2 is disclosed in an article by H. Chang, entitled Numerical and Experimental Comparison of 60V Vertical Double-Diffused MOSFETs and MOSFETs With A Trench-Gate Structure, Solid-State Electronics, Vol. 32, No. 3, pp. 247-251, (1989). However, in this device a lower-than-ideal uniform doping concentration in the drift region was required to compensate for the high concentration of field lines near the bottom corner of the trench when blocking high forward voltages. U.S. Pat. Nos. 5,637,989 and 5,742,076 and U.S. application Ser. No. 08/906,916, filed Aug. 6, 1997, the disclosures of which are hereby incorporated herein by reference, also disclose popular power semiconductor devices having vertical current carrying capability
In particular, U.S. Pat. No. 5,637,898 to Baliga discloses a preferred silicon field effect transistor which is commonly referred to as a graded-doped (GD) UMOSFET. As illustrated by FIG. 3 from the ""898 patent, a unit cell 100 of an integrated power semiconductor device field effect transistor may have a width xe2x80x9cWcxe2x80x9d of 1 xcexcm and comprise a highly doped drain layer 114 of first conductivity type (e.g., N+) substrate, a drift layer 112 of first conductivity type having a linearly graded doping concentration therein, a relatively thin base layer 116 of second conductivity type (e.g., P-type) and a highly doped source layer 118 of first conductivity type (e.g., N+). The drift layer 112 may be formed by epitaxially growing an N-type in-situ doped monocrystalline silicon layer having a thickness of 4 xcexcm on an N-type drain layer 114 having a thickness of 100 xcexcm and a doping concentration of greater than 1xc3x971018 cmxe2x88x923 (e.g. 1xc3x971019 cmxe2x88x923) therein. The drift layer 112 also has a linearly graded doping concentration therein with a maximum concentration of 3xc3x971017 cmxe2x88x923 at the N+/N junction with the drain layer 114, and a minimum concentration of 1xc3x971016 cmxe2x88x923 beginning at a distance 3 xcexcm from the N+/N junction (i.e., at a depth of 1 xcexcm) and continuing at a uniform level to the upper face. The base layer 116 may be formed by implanting a P-type dopant such as boron into the drift layer 112 at an energy of 100 keV and at a dose level of 1xc3x971014 cmxe2x88x922. The P-type dopant may then be diffused to a depth of 0.5 xcexcm into the drift layer 112. An N-type dopant such as arsenic may also be implanted at an energy of 50 keV and at dose level of 1xc3x971015 cmxe2x88x922. The N-type and P-type dopants can then be diffused simultaneously to a depth of 0.5 xcexcm and 1.0 xcexcm, respectively, to form a composite semiconductor substrate containing the drain, drift, base and source layers.
A stripe-shaped trench having a pair of opposing sidewalls 120a which extend in a third dimension (not shown) and a bottom 120b is then formed in the substrate. For a unit cell 100 having a width Wc of 1 xcexcm, the trench is preferably formed to have a width xe2x80x9cWtxe2x80x9d of 0.5 xcexcm at the end of processing. An insulated gate electrode, comprising a gate insulating region 124 and an electrically conductive gate 126 (e.g., polysilicon), is then formed in the trench. The portion of the gate insulating region 124 extending adjacent the trench bottom 120b and the drift layer 112 may have a thickness xe2x80x9cT1xe2x80x9d of about 2000 xc3x85 to inhibit the occurrence of high electric fields at the bottom of the trench and to provide a substantially uniform potential gradient along the trench sidewalls 120a. The portion of the gate insulating region 124 extending opposite the base layer 116 and the source layer 118 may have a thickness xe2x80x9cT2xe2x80x9d of about 500 xc3x85 to maintain the threshold voltage of the device at about 2-3 volts. Simulations of the unit cell 100 at a gate bias of 15 Volts confirm that a vertical silicon field effect transistor having a maximum blocking voltage capability of 60 Volts and a specific on-resistance (Rsp,on) of 40 xcexcxcexa9cm2, which is four (4) times smaller than the ideal specific on-resistance of 170 xcexcxcexa9cm2 for a 60 volt power UMOSFET, can be achieved. Notwithstanding these excellent characteristics, the transistor of FIG. 3 of the ""898 patent may suffer from a relatively low high-frequency figure-of-merit (HFOM) if the overall gate-to-drain capacitance (CGD) is too large. Improper edge termination of the MOSFET may also prevent the maximum blocking voltage from being achieved. Additional UMOSFETs having graded drift regions and trench-based source electrodes are also disclosed in U.S. Pat. No. 5,998,833 to Baliga, the disclosure of which is hereby incorporated herein by reference.
Power MOSFETs may also be used in power amplification applications (e.g., audio or rf). In these applications the linearity of the transfer characteristic (e.g., Idv. Vg) becomes very important in order to minimize signal distortion. Commercially available devices that are used in these power amplification applications are typically the LDMOS and gallium arsenide MESFETs. However, as described below, power MOSFETs including LDMOS transistors, may have non-linear characteristics that can lead to signal distortion. The physics of current saturation in power MOSFETs is described in a textbook by S. M. Sze entitled xe2x80x9cPhysics of Semiconductor Devices, Section 8.2.2, pages 438-451 (1981). As described in this textbook, the MOSFET typically works in one of two modes. At low drain voltages (when compared with the gate voltage), the MOSFET operates in a linear mode where the relationship between Id and Vg is substantially linear. Here, the transconductance (gm) is also independent of Vg:
gm=(Z/L)unsCoxVdxe2x80x83xe2x80x83(2) 
where Z and L are the channel width and length, respectively, uns is the channel mobility, Cox is the specific capacitance of the gate oxide, and Vd is the drain voltage. However, once the drain voltage increases and becomes comparable to the gate voltage (Vg), the MOSFET operates in the saturation mode as a result of channel pinch-off. When this occurs, the expression for transconductance can be expressed as:
gm=(Z/L)unsCox(Vgxe2x88x92Vth)xe2x80x83xe2x80x83(3) 
where Vg represents the gate voltage and Vth represents the threshold voltage of the MOSFET. Thus, as illustrated by equation (3), during saturation operation, the transconductance increases with increasing gate bias. This makes the relationship between the drain current (on the output side) and the gate voltage (on the input side) non-linear because the drain current increases as the square of the gate voltage. This non-linearity can lead to signal distortion in power amplifiers. In addition, once the voltage drop along the channel becomes large enough to produce a longitudinal electric field of more than about 1xc3x97104 V/cm while remaining below the gate voltage, the electrons in the channel move with reduced differential mobility because of carrier velocity saturation.
Thus, notwithstanding attempts to develop power MOSFETs for power switching and power amplification applications, there continues to be a need to develop power MOSFETs that can support high voltages and have improved electrical characteristics including highly linear transfer characteristics when supporting high voltages.
Vertical power devices according to embodiments of the present invention utilize retrograded-doped transition regions to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition regions and contribute to depletion of the transition regions during both forward on-state conduction and reverse blocking modes of operation.
A vertical power device (e.g., MOSFET) according to a first embodiment of the invention comprises a semiconductor substrate having first and second trenches and a drift region of first conductivity type (e.g., N-type) therein that extends into a mesa defined by and between the first and second trenches. The drift region is preferably nonuniformly doped and may have a retrograded doping profile relative to an upper surface of the substrate in which the first and second trenches are formed. In particular, the substrate may comprise a highly doped drain region of first conductivity type and a drift region that extends between the drain region and the upper surface. The doping profile in the drift region may decrease monotonically from a nonrectifying junction with the drain region to the upper surface of the substrate and an upper portion of the drift region may be uniformly doped at a relatively low level (e.g., 1xc3x971016 cmxe2x88x923). First and second insulated electrodes may also be provided in the first and second trenches. These first and second insulated electrodes may constitute trench-based source electrodes in a three-terminal device.
First and second base regions of second conductivity type (e.g., P-type) are also provided in the mesa. These base regions preferably extend adjacent sidewalls of the first and second trenches, respectively. First and second highly doped source regions of first conductivity type are also provided in the first and second base regions, respectively. An insulated gate electrode is provided that extends on the mesa. The insulated gate electrode is patterned so that the upper surface preferably defines an interface between the insulated gate electrode and the first and second base regions. Inversion-layer channels are formed within the first and second base regions during forward on-state conduction, by applying a gate bias of sufficient magnitude to the insulated gate electrode.
A transition region of first conductivity type is also provided in the mesa. This transition region preferably extends between the first and second base regions and extends to the interface with the insulated gate electrode. The transition region forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the upper surface. This doping profile has a peak doping concentration at a first depth relative to the upper surface, which may extend in a range from about 0.2 to 0.5 microns relative to the upper surface. Between the first depth and the upper surface, the doping profile is preferably monotonically decreasing in a direction towards the upper surface. A magnitude of a portion of a slope of this monotonically decreasing profile is preferably greater that 3xc3x971021 cmxe2x88x924. The establishment of a xe2x80x9cburiedxe2x80x9d peak at the first depth may be achieved by performing a single implant step at respective dose and energy levels or by performing multiple implant steps at respective dose levels and different energy levels. The peak dopant concentration in the transition region is preferably greater than at least about two (2) times the transition region dopant concentration at the upper surface. More preferably, the peak dopant concentration in the transition region is greater than about ten (10) times the transition region dopant concentration at the upper surface.
According to preferred aspects of power devices of the first embodiment, a product of the peak first conductivity type dopant concentration in the transition region (at the first depth) and a width of the transition region at the first depth is in a range between 1xc3x971012 cmxe2x88x922 and 7xc3x971012 cmxe2x88x922 and, more preferably, in a range between about 3.5xc3x971012 cmxe2x88x922 and about 6.5xc3x971012 cmxe2x88x922. Depending on unit cell design within an integrated multi-celled device, the product of the peak first conductivity type dopant concentration in the transition region and a width of the non-rectifying junction between the transition region and the drift region may also be in a range between 1xc3x971012 cmxe2x88x922 and 7xc3x971012 cmxe2x88x922. A product of the peak first conductivity type dopant concentration in the transition region, a width of the transition region at the first depth and a width of the mesa may also be set at a level less than 2xc3x971015 cmxe2x88x921. To achieve sufficient charge coupling in the drift region mesa, a product of the drift region mesa width and quantity of first conductivity type charge in a portion of the drift region mesa extending below the transition region is preferably in a range between 2xc3x97109 cmxe2x88x921 and 2xc3x971010 cmxe2x88x921.
According to further aspects of the first embodiment, enhanced forward on-state and reverse blocking characteristics can be achieved by including highly doped shielding regions of second conductivity type that extend in the mesa and on opposite sides of the transition region. In particular, a first shielding region of second conductivity type is provided that extends between the first base region and the drift region and is more highly doped than the first base region. Similarly, a second shielding region of second conductivity type is provided that extends between the second base region and the drift region and is more highly doped than the second base region. To provide depletion during forward on-state and reverse blocking modes of operation, the first and second shielding regions form respective P-N rectifying junctions with the transition region. High breakdown voltage capability may also be achieved by establishing a product of the peak first conductivity type dopant concentration in the transition region and a width between the first and second shielding regions in a range between 1xc3x971012 cmxe2x88x922 and 7xc3x971012 cmxe2x88x922.
Integrated vertical power devices according to a second embodiment of the invention preferably comprise active unit cells that provide forward on-state current and dummy cells that remove heat from the active cells during forward on-state conduction and support equivalent maximum reverse blocking voltages. According to the second embodiment, each integrated unit cell may comprise an active unit cell and one or more dummy unit cells. In addition to the first and second trenches, a third trench may be provided in the semiconductor substrate. The first and second trenches define an active mesa, in which an active unit cell is provided, and the second and third trenches define a dummy mesa therebetween in which a dummy unit cell is provided. A dummy base region of second conductivity type is provided in the dummy mesa preferably along with a dummy shielding region. The dummy base and shielding regions preferably extend across the dummy mesa and may be electrically connected to the first and second source regions within the active unit cell. In the event one or more dummy unit cells is provided, uniform reverse blocking voltage characteristics can be achieved by making the width of the mesa, in which the active unit cell is provided, equal to a width of the respective dummy mesa in which each of the dummy unit cells is provided. Alternatively, and in place of the third dummy base region, a field plate insulating layer may be provided on an upper surface of the dummy mesa and a third insulated electrode may be provided in the third trench. The source electrode may extend on the field plate insulating layer and is electrically connected to the first, second and third insulated electrodes within the trenches. In the event a field plate insulating layer is provided on the dummy mesa instead of using a dummy base region, the spacing between the first and second trenches need not necessarily equal the spacing between the second and third trenches in order to support maximum blocking voltages.
Additional embodiments of the present invention also include methods of forming vertical power devices. These methods preferably include implanting transition region dopants of first conductivity type at a first dose level and first energy level into a surface of a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent the surface. An insulated gate electrode may then be formed on the surface. The insulated gate electrode is preferably patterned so that it extends opposite the implanted transition region dopants. Shielding region dopants of second conductivity type are then implanted at a second dose level and second energy level into the surface. This implant step is preferably performed in a self-aligned manner with respect to the gate electrode, by using the gate electrode as an implant mask. Base region dopants of second conductivity type are also implanted at a third dose level and third energy level into the surface, using the gate electrode as an implant mask. Accordingly, the base and shielding region dopants are self-aligned to each other.
A thermal treatment step is then performed to drive the implanted transition, shielding and base region dopants into the substrate and define a transition region, first and second shielding regions on opposite sides of the transition region and first and second base regions on opposite sides of the transition region. The transition region extends into the drift region and has a vertically retrograded first conductivity type doping profile therein relative to the surface. This retrograded profile is achieved by establishing a buried peak dopant concentration sufficiently below the surface. The first and second shielding regions form respective P-N rectifying junctions with the transition region and the first and second base regions also form respective P-N rectifying junctions with the transition region. The dose and implant energies associated with the base and shielding region dopants are also selected so that the shielding regions are more highly doped relative to the base regions and extend deeper into the substrate.
According to a preferred aspect of this embodiment, the first dose and energy levels and a duration of the thermal treatment step are of sufficient magnitude that a product of a peak first conductivity type dopant concentration in the transition region and a width of the transition region, as measured between the first and second shielding regions, is in a range between 1xc3x971012 cmxe2x88x922 and 7xc3x971012 cmxe2x88x922. The first and second energy levels may also be set to cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of a peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.
The step of implanting shielding region dopants is also preferably preceded by the step of forming trenches in the semiconductor substrate and lining the trenches with trench insulating layers. Conductive regions are also formed on the trench insulating layers. These trench related steps may be performed before the step of implanting the transition region dopants. In this case, the transition region dopants are preferably implanted into the conductive regions within the trenches and into mesas that are defined by the trenches. According to still further preferred aspects of this embodiment, steps are also performed to increase maximum on-state current density within the power device by improving the configuration of the source contact. In particular, the source contact is formed on a sidewall of the trenches by etching back the trench insulating layers to expose the source, base and shielding regions and then forming a source contact that ohmically contacts the conductive regions and also contacts the source, base and shielding regions at the sidewall of each trench.
Vertical power MOSFETs according to further embodiments of the invention include a semiconductor substrate having a drift region of first conductivity type therein and an insulated gate electrode that extends on a first surface of the semiconductor substrate. A first base shielding region of second conductivity is provided that extends in the semiconductor substrate. The first base shielding region has a first lateral extent relative to a first end of the insulated gate electrode. A first base region of second conductivity type is also provided in the substrate. The first base region extends between the first base shielding region and the first surface. The first base region has a second lateral extent relative to the first end of the insulated gate electrode that is less than the first lateral extent. The power device also includes a first source region of first conductivity type that extends in and forms a P-N junction with the first base region. A transition region of first conductivity type is provided that extends between the drift region and a portion of the first surface extending opposite the insulated gate electrode. The transition region forms rectifying junctions with the first base region and the first base shielding region. An upper portion of the transition region has a vertically retrograded first conductivity type doping profile. The vertically retrograded first conductivity type doping profile may have a peak at a first depth relative to the first surface.
A second base region and a second base shielding region may also be provided in the substrate. In particular, the first and second base regions may be self-aligned to first and second opposing ends of the insulated gate electrode and may form respective P-N junctions with opposing sides of an upper portion of the transition region extending adjacent the first surface. The first and second base shielding regions are more highly doped than the first and second base regions and extend laterally towards each other in the semiconductor substrate to thereby constrict a neck of the upper portion of said transition region to a minimum width at a second depth relative to the first surface. The second depth is preferably greater than about 0.25 microns. A product of the peak first conductivity type dopant concentration in the transition region and a width of the transition region at the first depth is preferably in a range between about 1xc3x971012 cmxe2x88x922 and about 7xc3x971012 cmxe2x88x922, and more preferably in a range between about 3.5xc3x971012 cmxe2x88x922 and about 6.5xc3x971012 cmxe2x88x922.
Methods of forming these vertical MOSFETs may include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is then formed on the first surface. After the gate electrode has been formed, base shielding region dopants of second conductivity type are implanted at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask. The peak concentration of implanted base shielding region dopants is sufficiently spaced from the first surface that buried base shielding regions can be formed with the characteristics described herein. The semiconductor substrate is then annealed to partially drive the base shielding region dopants vertically into the transition region and laterally underneath the gate electrode. This annealing step results in the definition of first and second intermediate shielding regions. Base region dopants of second conductivity type are then implanted at a relatively low dose and low energy level into upper portions of the first and second intermediate shielding regions. During this implant step, the gate electrode is used again as an implant mask in order to provide a self-aligned feature. Another annealing step is then performed to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions. During this annealing step, the base shielding region dopants are also driven laterally and vertically to substantially their full and final depth within the substrate. Based on the early implant and multiple annealing steps, first and second base shielding regions are defined that constrict a neck of the upper portion of the transition region to a minimum width at a depth corresponding to the depth at which the original peak concentration of implanted base shielding region dopants is achieved. First and second source regions are then formed in the first and second base regions, respectively.
Power devices according to still further embodiments of the present invention include a semiconductor substrate having a drift region of first conductivity type therein and transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. This transition region has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface. First and second shielding regions of second conductivity type are also provided. These shielding regions extend in the drift region and define respective P-N junctions with the transition region. In particular, the first and second shielding regions extend laterally towards each other in a manner that constricts a neck of the transition region to a minimum width at a second depth relative to the first surface. An anode electrode may also be provided on the first surface of the semiconductor substrate. This anode electrode defines a Schottky rectifying junction with the transition region. According to preferred aspects of these embodiments, the transition region is designed so that a product of the peak first conductivity type dopant concentration in the transition region and a width of the transition region at the first depth is in a range between about 1xc3x971012 cmxe2x88x922 and about 7xc3x971012 cmxe2x88x922 and, more preferably, in a range between about 3.5xc3x971012 cmxe2x88x922 and about 6.5xc3x971012 cmxe2x88x922.